Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays.
As chip capacity continues to increase, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, a FPGA is a programmable logic device (PLD) that has a number of electronic gates approaching that of large ASICs, however a FPGA is significantly more flexible. Notably, FPGAs can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or “plugin card.” Advancement of FPGA technology has led to the development of FPGA-based system-on-chips (SoC) including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, an embedded processor SoC would include all required ancillary electronics within the chip. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. A SoC could also include multiple processing modules coupled to each other via a bus or several busses. It should also be understood herein that “FPGA-based embedded processor SoCs” are a specific subset of FPGA-based SoCs that would include their own processors.
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, it is necessary for them to acquire or develop system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC. More generally, the IP cores can form one or more of the processing modules in an FPGA-based SoCs. The processing modules can either be hardware or software based.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. One of the challenges includes communication among multiple hardware and software processors embedded in a FPGA-based SoC. Typically, such communication occurs over a bus. Unfortunately, the embedded processors in a FPGA-based SoC are treated as a separate computer requiring the use of a C compiler and a runtime stack or a conventional heap data structure. Additionally, existing FPGA-based embedded processor SoCs require several programming languages to specify the entire design system. In particular, a system may require both a high-level software language and a hardware descriptive language (HDL) to define the hardware in the FPGA for the system solution. Furthermore, such existing systems require a Real Time Operation System (RTOS). FPGA based embedded processor SoCs are being introduced into the market, but there are no solutions that allow users to customize the system, the hardware and software processing modules and the associated software, nor are there systems that enable a user to tradeoff a function that is implemented in hardware (FPGA fabric) or software (running on the embedded processor). Nor is there a system that is optimized for a soft-fabric processor (or “soft” processor) to be implemented efficiently in the fabric of a field programmable gate array. It would be desirable to have a reduced instruction set computer (RISC) core that is intended for efficient physical implementation using an FPGA, well-balanced for embedded applications within the FPGA fabric, and able to be synthesized from HDL code with high performance. With this in mind, the RISC core would be ideally implemented with efficient resource utilization, small footprint utilization within the FPGA, high performance, as well as capable of supporting the unique problems of realtime software.